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general description the MAX7036 low-cost receiver is designed to receive amplitude-shift-keyed (ask) and on-off-keyed (ook) data in the 300mhz to 450mhz frequency range. the receiver has an rf input signal range of -109dbm to 0dbm. the MAX7036 requires few external components and has a power-down pin to put it in a low-current sleep mode, making it ideal for cost- and power-sensitive applications. the low-noise amplifier (lna), phase- locked loop (pll), mixer, if filter, received-signal- strength indicator (rssi), and baseband sections are all on-chip. the MAX7036 uses a very-low intermediate frequency (vlif) architecture. the MAX7036 integrates the if filter on-chip and therefore eliminates an external ceramic filter, reducing the bill-of-materials cost. the device also contains an on-chip automatic gain control (agc) that reduces the lna gain by 30db when the input signal power is large. the MAX7036 operates from either a 5v or a 3.3v power supply and draws 5.5ma (typ) of current. the MAX7036 is available in a 20-pin thin qfn pack- age with an exposed pad and is specified over the aec-q100 level 2 (-40? to +105?) temperature range. applications low-cost rke garage door openers remote controls home automation sensor networks security systems features ask/ook modulation < 250? enable turn-on time on-chip pll, vco, mixer, if, baseband low if (200khz nominal) 5.5ma dc current 1? standby current 3.3v/5v operation small 20-pin thin qfn package with an exposed pad MAX7036 300mhz to 450mhz ask receiver with internal if filter ________________________________________________________________ maxim integrated products 1 MAX7036 thin qfn 5mm x 5mm top view 19 20 ep* + 18 17 7 6 8 xtal2 avdd lnain 9 enable opp dvdd ifc3 dffb 12 pdout 45 15 14 12 11 v dd dataout ifc2 mixin1 mixin2 lnaout xtal1 dcoc 3 13 dsn 16 10 ifc1 dsp pin configuration ordering information 19-4386; rev 0; 3/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX7036gtp/v+ -40? to +105? 20 thin qfn-ep* /v denotes an automative qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad.
MAX7036 300mhz to 450mhz ask receiver with internal if filter 2 _______________________________________________________________________________________ absolute maximum ratings 3.3v dc electrical characteristics ( typical application circuit , 50 system impedance, v avdd = v dvdd = v dd = 3.0v to 3.6v, f rf = 300mhz to 450mhz, t a = -40? to +105?, unless otherwise noted. typical values are at v avdd = v dvdd = v dd = 3.3v, t a = +25?, unless otherwise noted.) (100% tested at t a = +105?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +6.0v avdd to gnd........................................................-0.3v to +4.0v dvdd to gnd........................................................-0.3v to +4.0v enable to gnd.........................................-0.3v to (v dd + 0.3v) lnain to gnd .......................................................-0.3v to +1.2v all other pins to gnd.............................-0.3v to (v dvdd + 0.3v) continuous power dissipation (t a = +70?) 20-pin tqfn (derate 20.8mw/? above +70?) ....1666.7mw junction-to-case thermal resistance ( ja ) (note 1) 20-pin tqfn...................................................................2?/w junction-to-ambient thermal resistance ( ja ) (note 1) 20-pin tqfn.................................................................48?/w operating temperature range .........................-40? to +105? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply voltage v dd v avdd = v dvdd = v dd 3.0 3.3 3.6 v f rf = 315mhz 5.3 6.7 f rf = 433mhz 5.8 7.3 ma supply current i in t a < +105? deep-sleep mode, v enable = 0 1 2.7 ? digital input (enable) input high voltage v ih v avdd = v dvdd = v dd v dd - 0.4 v input low voltage v il v avdd = v dvdd = v dd 0.4 v input current i enable 0 v enable v dd 20 ? digital output (dataout) output low voltage v ol i sink = 100? 0.4 v output high voltage v oh i source = 100? v dd - 0.4 v note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a single- layer board. for detailed information on package thermal considerations, go to www.maxim-ic.com/thermal-tutorial .
MAX7036 300mhz to 450mhz ask receiver with internal if filter _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units supply voltage v dd 4.5 5.0 5.5 v f rf = 315mhz 5.4 6.8 f rf = 433mhz 5.9 7.4 ma supply current i in t a < +105? deep-sleep mode, v enable = 0 1 3.4 ? digital input (enable) input high voltage v ih v avdd = v dvdd v dd - 0.4 v input low voltage v il v avdd = v dvdd 0.4 v input current i enable 0 v enable v dd 20 ? digital output (dataout) output low voltage v ol i sink = 100? 0.4 v output high voltage v oh i source = 100? v dd - 0.4 v 5.0v dc electrical characteristics ( typical application circuit , 50 system impedance, v dd = 4.5v to 5.5v, f rf = 300mhz to 450mhz, t a = -40? to +105?, unless otherwise noted. typical values are at v dd = 5.0v, t a = +25?, unless otherwise noted.) (100% tested at t a = +105?.) ac electrical characteristics ( typical application circuit , 50 system impedance, v avdd = v dvdd = v dd = 3.0v to 3.6v, f rf = 300mhz to 450mhz, t a = -40? to +105?, unless otherwise noted. typical values are at v avdd = v dvdd = v dd = 3.3v, t a = +25?, f rf = 315mhz, unless otherwise noted.) (100% tested at t a = +105?.) parameter symbol conditions min typ max units receiver input frequency range f rf 300 450 mhz maximum receiver input level p rfin 0 dbm f rf = 315mhz -109 sensitivity (note 2) f rf = 433mhz -107 dbm enable power on (v dd > 3.0v) 250 ? power-on time t on time for valid rssi output, does not include baseband filter settling v dd power on 1 ms agc hysteresis 5db agc low gain-to-high gain switching time 13 ms
MAX7036 300mhz to 450mhz ask receiver with internal if filter 4 _______________________________________________________________________________________ ac electrical characteristics (continued) ( typical application circuit , 50 system impedance, v avdd = v dvdd = v dd = 3.0v to 3.6v, f rf = 300mhz to 450mhz, t a = -40? to +105?, unless otherwise noted. typical values are at v avdd = v dvdd = v dd = 3.3v, t a = +25?, f rf = 315mhz, unless otherwise noted.) (100% tested at t a = +105?.) parameter symbol conditions min typ max units lna/mixer f rf = 315mhz 0.4 - j5.6 lna input impedance z inlna normalized to 50 f rf = 433mhz 0.4 - j4.0 lo signal feedthrough to antenna -75 dbm voltage gain reduction low-gain mode, agc enabled 29 db high-gain lna mode 55 lna/mixer voltage gain low-gain lna mode 26 db 3db cutoff frequency bw if set by capacitors on ifc1 and ifc2 (see the typical application circuit ) 400 khz rssi linearity ?.5 db rssi dynamic range includes agc 80 db p rfin < -120dbm 1.34 rssi level p rfin > 0dbm, agc enabled 2.35 v intermediate frequency f if 200 khz maximum data-filter bandwidth bw df 50 khz maximum data-slicer bandwidth bw ds 100 khz maximum peak detector bandwidth 50 khz manchester coded 33 maximum data rate nonreturn to zero (nrz) 66 kbps crystal frequency f xtal 9.36 14.06 mhz crystal load capacitance c load 10 pf note 2: ber = 2 x 10 -3 , manchester coded, data rate = 4kbps. if bandwidth = 400khz.
MAX7036 300mhz to 450mhz ask receiver with internal if filter _______________________________________________________________________________________ 5 supply current vs. supply voltage (3.3v operation) MAX7036 toc01 supply voltage (v) supply current (ma) 3.4 3.3 3.2 3.1 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.8 3.0 3.6 3.5 t a = -40 c t a = +25 c t a = +85 c t a = +105 c v avdd = v dvdd = v dd supply current vs. supply voltage (5.0v operation) MAX7036 toc02 supply voltage (v) supply current (ma) 5.3 5.1 4.9 4.7 5.05 5.10 5.15 5.20 5.25 5.30 5.35 5.40 5.45 5.00 4.5 5.5 5.0v application circuit t a = +105 c t a = -40 c t a = +85 c t a = +25 supply current vs. rf frequency MAX7036 toc03 rf frequency (mhz) supply current (ma) 450 400 350 300 4.5 5.0 5.5 6.0 6.5 7.0 4.0 250 500 t a = +105 c t a = -40 c t a = +85 c t a = +25 p rf = -80dbm bit error rate vs. peak rf input power MAX7036 toc04 peak rf input power (dbm) bit error rate (%) -105 -110 -115 -120 0.01 0.1 1 10 100 0.001 -125 f rf = 315mhz f rf = 433mhz sensitivity vs. temperature MAX7036 toc05 temperature ( c) sensitivity (dbm) 60 85 105 35 10 -15 -108.5 -108.0 -107.5 -107.0 -106.5 -106.0 -110.5 -110.0 -109.5 -109.0 -40 f rf = 315mhz f rf = 433mhz ber = 0.2% data rate = 4kbps manchester rssi vs. input power MAX7036 toc06 input power (dbm) rssi (v) -40 -20 0 -60 -80 -100 1.4 1.6 1.8 2.0 2.2 2.4 1.2 -120 f rf = 433mhz if = 200khz lna/mixer voltage gain vs. if frequency MAX7036 toc07 if frequency (khz) lna/mixer voltage gain (db) 800 1000 600 400 200 44 46 48 50 52 54 56 58 60 40 42 0 f rf = 433.92mhz p rf = -71dbm s 11 smith chart plot of rfin (315mhz circuit) MAX7036 toc08 s 11 = 7.9729 - j0.6085 at f rf = 315mhz s 11 smith chart plot of rfin (433mhz circuit) MAX7036 toc09 s 11 = 6.5175 - j5.5849 at f rf = 433mhz typical operating characteristics ( typical application circuit , v avdd = v dd = v dvdd = 3.3v, f rf = 315mhz, t a = +25?, unless otherwise noted.)
MAX7036 300mhz to 450mhz ask receiver with internal if filter 6 _______________________________________________________________________________________ pin description typical operating characteristics (continued) ( typical application circuit , v avdd = v dd = v dvdd = 3.3v, f rf = 315mhz, t a = +25?, unless otherwise noted.) pin name function 1 enable enable input. internally pulled down to ground. set v enable = v dd for normal operation. 2 xtal2 crystal input 2. connect an external crystal from xtal2 to xtal1. can also be driven with an ac- coupled external reference oscillator (see the crystal oscillator section). 3 xtal1 crystal input 1. connect an external crystal from xtal2 to xtal1. bypass to gnd if xtal2 is driven from an ac-coupled external reference (see the phase-locked loop section). 4 avdd positive analog supply voltage. connect to dvdd. bypass to gnd with a 0.1? capacitor as close as possible to the device (see the typical application circuit ). for 5.0v operation, avdd is internally connected to an on-chip 3.2v ldo regulator. for 3.3v operation, connect avdd to v dd . 5 lnain low-noise amplifier input. must be ac-coupled (see the low-noise amplifier section). 6 lnaout low-noise amplifier output. must be connected to avdd through a parallel lc tank circuit. ac- couple to mixin2 (see the low-noise amplifier section). 7 mixin2 2nd differential mixer input. connect to the lnaout side of the lc tank filter through a 100pf capacitor (see the typical application circuit ). 8 mixin1 1st differential mixer input. connect to the avdd side of the lc tank filter through a 100pf capacitor (see the typical application circuit ). 9 ifc2 if fi l ter c ap aci tor c onnecti on 2. thi s i s for the s al l en- key if fi l ter . c onnect a cap aci tor fr om ifc 2 to gn d . the val ue of the cap aci tor i s d eter m i ned b y the if fi l ter b and w i d th ( see the typical application circuit ) . 10 ifc1 if fi l ter c ap aci tor c onnecti on 1. thi s i s for the s al l en- key if fi l ter . c onnect a cap aci tor fr om ifc 1 to ifc 3. the val ue of the cap aci tor i s d eter m i ned b y the if fi l ter b and w i d th ( see the typical application circuit ) . 11 ifc3 if fi l ter c ap aci tor c onnecti on 3. thi s i s for the s al l en- key if fi l ter . c onnect a cap aci tor fr om ifc 3 to ifc 1. the val ue of the cap aci tor i s d eter m i ned b y the if fi l ter b and w i d th ( see the typical application circuit ) . 12 dvdd positive digital supply voltage input. connect to avdd. bypass to gnd with a 0.01? capacitor as close as possible to the device (see the typical application circuit ). regulator voltage vs. regulator current MAX7036 toc10 regulator current (ma) regulator voltage (v) 20 25 15 10 5 3.05 3.10 3.15 3.00 0 t a = -40 c t a = +25 c t a = +85 c t a = +105 c v dd = 5v, +5v circuit phase noise vs. offset frequency MAX7036 toc11 offset frequency (khz) phase noise (dbc/hz) 100 10,000 1 -70 -60 -50 -120 -110 -100 -90 -80 0.01 f rf = 315mhz phase noise vs. offset frequency MAX7036 toc12 offset frequency (khz) phase noise (dbc/hz) 100 10,000 1 -70 -60 -50 -120 -110 -100 -90 -80 0.01 f rf = 433mhz
MAX7036 300mhz to 450mhz ask receiver with internal if filter _______________________________________________________________________________________ 7 functional diagram pin description (continued) pin name function 13 dcoc dc offset capacitor connection. this is for the rssi amplifier. connect a 1? capacitor from this pin to ground (see the typical application circuit ). 14 opp noninverting op-amp input. this is for the sallen-key data filter. connect a capacitor from this pin to gnd. the value of the capacitor is determined by the data-filter bandwidth. 15 dffb data-filter feedback input. input for the feedback of the sallen-key data filter. connect a capacitor from this pin to dsp. the value of the capacitor is determined by the data-filter bandwidth. 16 dsp positive data-slicer input. connect a capacitor from this pin to dffb. the value of the capacitor is determined by the data-filter bandwidth. 17 dsn negative data-slicer input 18 pdout peak-detector output 19 v dd power-supply voltage input. for 5.0v operation, v dd is the input to an on-chip voltage regulator whose 3.2v output drives avdd. bypass to ground with a 0.1? capacitor as close as possible to the device (see the typical application circuit ). 20 dataout digital baseband data output ?p exposed pad. internally connected to ground. connect to a large ground plane using multiple vias to maximize thermal and electrical performance. MAX7036 ep* *exposed pad. connect to gnd. 3.2v regulator peak detector ref ref agc dataout dsn pdout dsp opp dffb lnaout mixin1 mixin2 xtal1 xtal2 enable v dd avdd dvdd lnain ifc1 ifc2 ifc3 dcoc pll 3 2 1 19 4 12 5 687 10 9 13 11 20 17 18 16 14 15
MAX7036 detailed description the MAX7036 cmos rf receiver, and a few external components, provide the complete receiver chain from the antenna to the digital output data. depending on signal power and component selection, data rates as high as 33kbps manchester (66kbps nrz) can be achieved. the MAX7036 is designed to receive binary ask/ook data modulated in the 300mhz to 450mhz frequency range. ask modulation uses a difference in amplitude of the carrier to represent digital data. voltage regulator for operation with a single 3.0v to 3.6v supply voltage, connect avdd, dvdd, and v dd to the supply voltage. for operation with a single 4.5v to 5.5v supply voltage, connect v dd to the supply voltage. an on-chip voltage regulator drives the avdd pin to approximately 3.2v. for proper operation, connect dvdd and avdd togeth- er. bypass v dd and avdd to gnd with 0.1? capaci- tors placed as close as possible to the device. bypass dvdd to gnd with a 0.01? capacitor (see the typical application circuit ). low-noise amplifier the lna is an nmos cascode amplifier. the lna and mixer have a combined 55db voltage gain. the gain and noise figures are dependent on both the antenna- matching network at the lna input and the lc tank net- work between the lna output and the mixer inputs. l2 and c1 comprise the lc tank filter connected to lnaout (see the typical application circuit ). l2 also serves as a bias inductor to lnaout. bypass the power-supply side of l2 to gnd with a capacitor that provides a low-impedance path at the rf carrier fre- quency (e.g., 220pf). select l2 and c1 to resonate at the desired rf input frequency. the resonant frequen- cy is given by: where l total = l2 + l parasitics and c total = c1 + c parasitics . l parasitics and c parasitics include inductance and capacitance of the pcb traces, package pins, mixer input impedance, lna output impedance, etc. at high frequencies, these parasitics can have a dramatic effect on the tank filter center frequency and must not be ignored. the total parasitic capacitance is generally 4pf to 6pf. adjust l2 and c1 accordingly to achieve the desired tank center frequency. automatic gain control (agc) the agc circuit monitors the rssi output. the agc switches to its low-gain state when the rssi output reaches 2.2v. the agc gain reduction is typically 29db, corresponding to an rssi voltage drop of 435mv. the lna resumes high-gain mode when the rssi level drops back below 1.67v for 13ms for 315mhz and 10ms for 433mhz operation. the agc has a hysteresis of 5db. with this agc function, the MAX7036 can reliably produce an ask output for rf input levels up to 0dbm, with modulation depth of 30db. mixer the mixer cell is a double-balanced mixer that performs a downconversion of the rf input to a typical if of 200khz from either a high-side or a low-side injected lo. the mixer output drives the input of the on-chip if filter. phase-locked loop (pll) the pll block contains a phase detector, charge pump, integrated loop filter, vco, asynchronous clock dividers, and crystal-oscillator driver. besides the crys- tal, this pll does not require any external components. the vco generates the lo. the relationship between the rf, if, and reference frequencies is given by: where f lo = f rf ? if received-signal-strength indicator (rssi) the rssi circuit provides a dc output proportional to the logarithm of the input power level. rssi output volt- age has a slope of about 14.5mv/db (of input power).the rssi monotonic dynamic range exceeds 80db. this includes the 30db of agc. applications information crystal oscillator the crystal (xtal) oscillator in the MAX7036 is designed to present a capacitance of approximately 4pf between xtal1 and xtal2. in most cases, this corresponds to a 6pf load capacitance applied to the external crystal when typical pcb parasitics are added. the MAX7036 is designed to operate with a typical 10pf load capacitance crystal. it is very important to use a crystal with a load capacitance equal to the capacitance of the MAX7036 crystal oscillator plus pcb parasitics. if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing f f ref lo = 32 f lc rf total total = 1 2 300mhz to 450mhz ask receiver with internal if filter 8 _______________________________________________________________________________________
an error in the reference frequency. a crystal designed to operate at a higher load capacitance than the value specified for the oscillator is always pulled higher in fre- quency. adding capacitance to increase the load capacitance on the crystal increases the start-up time and may prevent oscillation altogether. in actuality, the oscillator pulls every crystal. the crys- tal? natural frequency is really below its specified fre- quency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency is pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded, as specified (i.e., c load = c spec ), the frequency pulling equals zero. it is possible to use an external reference oscillator in place of a crystal to drive the vco. ac-couple the exter- nal oscillator to xtal2 with a 1000pf capacitor. drive xtal2 with a signal level of approximately -10dbm. ac- couple xtal1 to ground with a 1000pf capacitor. if filter the if filter is a 2nd-order butterworth lowpass filter preceded by a low-frequency dc block. the lowpass filter is implemented as a sallen-key filter using an internal op amp and two on-chip 22k resistors. the pole locations are set by the combination of the on-chip resistors and two external capacitors (c9 and c10, figure 1). the values of these two capacitors for a 3db cutoff frequency of 400khz are given below: because the stray shunt capacitance at each of the pins (ifc1 and ifc2) on a typical pcb is approximately 2pf, choose the value of the external capacitors to be approximately 2pf lower than the desired total capaci- tance. therefore, the practical values for c9 and c10 are 22pf and 10pf, respectively. data filter the data filter is implemented as a 2nd-order lowpass sallen-key filter. the pole locations are set by the combi- nation of two on-chip resistors and two external capaci- tors. adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. set the corner frequency to approximately 1.5 times the fastest manchester expected data rate from the transmitter. keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. the configuration shown in figure 2 can create a butterworth or bessel response. the butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works with the coefficients in table 1. where f c is the desired corner frequency. c a kf c 6 4 100 = ()() () c b ak f c 5 100 = ()() () c rf k c 9 1 1 414 1 1 414 22 3 14 4 = ( )()() () = ()()() . .. 0 00 26 10 1 2 828 1 2 828 khz pf c rf c () = = ( )()() () = ( . . ) )( )( )( ) = 22 3 14 400 13 kkhz pf . f c cc cc p m case load case spec = + ? + ? ? ? ? ? ? ? ? 2 11 10 6 MAX7036 300mhz to 450mhz ask receiver with internal if filter _______________________________________________________________________________________ 9 MAX7036 c9 22k 22k c10 10 ifc1 9 ifc2 11 ifc3 figure 1. sallen-key lowpass if filter
MAX7036 for example, to choose a butterworth filter response with a corner frequency of 6khz: choosing standard capacitor values changes c5 to 390pf and c6 to 180pf, as shown in the typical application circuit . data slicer the data slicer takes the analog output of the data filter and converts it to a digital signal. this is achieved by using a comparator and comparing the analog input to a threshold voltage. one input is supplied by the data- filter output. both comparator inputs are accessible off chip to allow for different methods of generating the slicing threshold, which is applied to the second com- parator input. the suggested data-slicer configuration uses a resistor (r1) connected between dsn and dsp with a capaci- tor (c4) from dsn to gnd (figure 3). this configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the values of r1 and c4 affect how fast the threshold tracks to the analog ampli- tude. be sure to keep the corner frequency of the rc circuit much lower than the lowest expected data rate. note that a long string of zeros or ones can cause the threshold to drift. this configuration works best if a coding scheme (e.g., manchester coding, which has an equal number of zeros and ones) is used. peak detector the peak-detector output (pdout), in conjunction with an external rc filter, creates a dc output voltage equal to the peak value of the data signal. the resistor pro- vides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. the peak detector can be used for at least two functions. first, it can serve as an rssi for ask modulation. second, it can be used for faster data-slicer response by adding it to the threshold pin (dsn) on the data-slicer comparator (figure 4). the two capacitors in this circuit should be equal, and the peak detector resistor should be approximately 10 c kkhz pf c 5 1 000 1 414 100 3 14 6 375 6 = ()( )()() = = . .. 1 1 414 4 100 3 14 6 186 . . ()( )( )( ) = kkhz pf 300mhz to 450mhz ask receiver with internal if filter 10 ______________________________________________________________________________________ filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618 table 1. coefficients to calculate c5 and c6 16 dsp c6 c5 r df2 100k r df1 100k rssi 14 opp 15 dffb MAX7036 figure 2. sallen-key lowpass data filter 20 c4 r1 17 dsn 16 dsp MAX7036 data out data slicer data filter figure 3. generating data-slicer threshold
times larger than the resistor in the rc smoothing cir- cuit between dsp and dsn. this circuit will provide an instantaneous jump of one-half of the dsp increase from ?o signal?voltage to peak voltage, which then decays with the same time constant as that of the threshold build-up from the rc smoothing circuit. the dc slicing voltage at dsn is slightly higher (by the ratio of the two resistors in the circuit) than it would be with- out the speed-up circuit. always provide a capacitive path from the pdout pin to ground when using the peak-detector output. layout considerations a properly designed pcb is an essential part of any rf/microwave circuit. on high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. at high frequencies, trace lengths that are /10 or longer act as antennas. keeping the traces short also reduces parasitic induc- tance. generally, 1in of a pcb trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace con- necting a 100nh inductor adds an extra 10nh of induc- tance or 10%. to reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. also, use low-inductance connections to ground on all gnd pins, and place decoupling capacitors close to all power-supply connections. MAX7036 300mhz to 450mhz ask receiver with internal if filter ______________________________________________________________________________________ 11 component f rf = 315mhz f rf = 433.92mhz c1 4.7pf 2.7pf c2 100pf 100pf c3 100pf 100pf c4 0.1? 0.1? c5 390pf 390pf c6 180pf 180pf c7 1? 1? c8 0.01? 0.01? c9 22pf 22pf c10 10pf 10pf c11 0.1? 0.1? c12 220pf 220pf c13 10pf 10pf c14 10pf 10pf c15 100pf 100pf c16 0.1? 0.1? l1 100nh 47nh l2 27nh 15nh r1 22k 22k y1 9.8375mhz 13.55375mhz 20 c4 r1 17 dsn 16 dsp MAX7036 data out data slicer data filter 18 pdout figure 4. using pdout for faster startup table 2. component values
MAX7036 300mhz to 450mhz ask receiver with internal if filter maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . typical application circuit chip information process: cmos enable xtal2 xtal1 dffb opp dcoc ifc3 dvdd lnain avdd lnaout mixin2 mixin1 ifc1 ifc2 dataout v dd pdout dsp dsn +5v MAX7036 l1 l2 y1 c14 c13 c15 c16 c5 c11 r1 c2 c9 c1 c12 c3 c4 c10 c8 c6 c7 connect avdd, dvdd, and v dd together for 3.3v applications. package type package code document no. 20 thin qfn-ep t2055+3 21-0140

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